In semiconductor devices that store random access data, a memory controller is typically provided to coordinate the writing and reading of that data to and from a memory device. This memory controller coordinates when the memory device will be active, when it will be written to, when it will be read from, and what specific memory elements (i.e., bit storage elements) within the memory will be accessed.
In dynamic random access memories (DRAMs), especially synchronous DRAMs (SDRAM, double data rate (DDR) SDRAM, mobile SDRAM, mobile DDR SDRAM, etc.), or the like, each memory chip receives a signal that indicates whether the memory element will be active or not. This signal is typically called a chip select (CS) signal. It is set to have a first value (e.g., low or logical “0”) when the memory chip (or memory die) is to be active, and is set to have a second value (e.g., high or logical “1”) when the memory element is to be inactive. Generally a memory element will be kept inactive except when it is being actively accessed for a read or a write operation.
As semiconductor devices continue to increase in speed and complexity, their need for larger amounts of memory (i.e. memory density) likewise increases. In some devices a single large memory chip can be used to obtain a desired memory size. In other devices multiple smaller memory chips can be used in place of a single large memory die. The smaller memory chips can cost less to manufacture than larger devices, such that two memory chips of a given size can cost less than a single larger memory chip of a corresponding memory size. The single larger memory chip can also be too big to fit into the given package size which typically follows the value set by a standard so that it's realization can be delayed until the next advanced technology is available.
When multiple smaller memory chips are used to achieve a desired memory size, however, it is necessary to provide a separate chip select signal for each individual memory chip. This is because only one memory chip should be activated at any given time. Since each memory chip is a separate memory device in its own right, each must be selected by its own respective chip select line.
As a result, when multiple memory chips are used to achieve a desired memory size, a memory controller must generate a number of chip select signals equal to the number of memory chips used. And because a chip select signal is not generally multiplexed on a line, the memory controller must have a separate output pin for each chip select signal.